Author Publications

2011

Klumperink, Eric and Dutta, Ramen and Ru, Zhiyu and Nauta, Bram and Gao, Xiang (2011) Jitter-Power minimization of digital frequency synthesis architectures. In: IEEE International Symposium on Circuits and Systems, ISCAS 2011, 15-18 May 2011, Rio de Janeiro, Brazil.

2010

Dutta, R. and Bhattacharyya, T.K. and Gao, X. and Klumperink, E.A.M. (2010) Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. In: 23th International Conference on VLSI Design, VLSID 2010, 3-7 Jan 2010, Bangalore, India.

Gao, Xiang and Klumperink, Eric and Socci, Gerard and Bohsali, Mounhir and Nauta, Bram (2010) A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power. In: IEEE Symposium on VLSI Circuits, VLSI 2010, 16-18 June 2010, Hawai, Honolulu.

Gao, Xiang (2010) Low jitter low power phase locked loops using sub-sampling phase detection. thesis.

Gao, Xiang and Klumperink, Eric A.M. and Nauta, Bram and Bohsali, Mounhir and Kiaei, Ali and Socci, Gerard and Djabbari, Ali (2010) Phase-locked loop including sampling phase detector and charge pump with pulse width control. Patent.

Gao, Xiang and Klumperink, Eric A.M. and Socci, Gerard and Bohsali, Mounhir and Nauta, Bram (2010) Spur-reduction techniques for PLLs using sub-sampling phase detection. In: IEEE International Solid-State Circuits Conference, ISSCC 2010, 7-11 Feb 2010, San Francisco, USA.

Gao, Xiang and Klumperink, Eric A.M. and Socci, Gerard and Bohsali, Mounhir and Nauta, Bram (2010) Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. IEEE Journal of Solid-State Circuits, 45 (9). pp. 1809-1821. ISSN 0018-9200

2009

Gao, X. and Klumperink, E.A.M. and Bohsali, M. and Nauta, B. (2009) A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS. In: IEEE International Solid-State Circuits Conference, 8-12 February 2009, San Francisco.

Gao, X. and Klumperink, E.A.M. and Geraedts, P.F.J. and Nauta, B. (2009) Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. IEEE Transactions on Circuits and Systems II - Express Briefs, 56 (2). pp. 117-121. ISSN 1549-7747

Gao, X. and Klumperink, Eric A.M. and Bohsali, Mounhir and Nauta, Bram (2009) A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2. IEEE Journal of Solid-State Circuits, 44 (12). pp. 3253-3263. ISSN 0018-9200

Gao, Xiang and Klumperink, Eric A.M. and Boshali, Mounir and Nauta, Bram (2009) A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise. In: ProRISC 2009, Annual Workshop on Circuits, Systems and Signal Processing, 26-27 Nov 2009, Veldhoven, the Netherlands.

Klumperink, Eric A.M. and Gao, Xiang and Nauta, Bram (2009) Polyphase Multipath Circuits for Cognitive Radio and Flexible Multi-phase Clock Generation. In: Circuits and Systems for Future Generations of Wireless Communications. Integrated Circuits and Systems . Springer Netherlands, pp. 145-168. ISBN 9781402099175

2008

Gao, Xiang and Klumperink, Eric A.M. and Nauta, Bram (2008) Advantages of Shift Registers over DLLs for Flexible Low Jitter Multiphase Clock Generation. IEEE Transactions on Circuits and Systems II - Express Briefs, 55 (3). pp. 244-248. ISSN 1549-7747

2007

Gao, X. and Klumperink, E.A.M. and Nauta, B. (2007) Low-Jitter Multi-phase Clock Generation: a Comparison between DLLs and Shift Registers. In: IEEE International Symposium on Circuits and Systems, ISCAS 2007, 27-30 May 2007, New Orleans, LA.

Gao, X. and Klumperink, E.A.M. and Nauta, B. (2007) Comparing DLLs and Shift Registers for Low-Jitter Multi-phase Clock Generation. In: ProRISC 2007, 18th Annual Workshop on Circuits, Systems and Signal Processing, 29-30 Nov 2007, Veldhoven, the Netherlands.

2006

Gao, X. (2006) Multi-phase clock generation for multi-path poly-phase transceivers. [Masters Thesis]