Author Publications

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Number of items: 12.

Article

Beek, Remco C.H van de and Vaucher, Cicero S. and Leenaerts, Domine M.W. and Klumperink, Eric A.M. and Nauta, Bram (2004) A 2.5-to-10 GHz Clock Multiplier Unit with 0.22 ps RMS jitter. IEEE Journal of Solid-State Circuits, 39 (11). pp. 1862-1872. ISSN 0018-9200

Beek, Remco C.H van de and Vaucher, Cicero S. and Leenaerts, Domine M.W. and Klumperink, Eric A.M. and Nauta, Bram (2004) A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 39 (11). pp. 1862-1872. ISSN 0018-9200

Beek, Remco C.H. van de and Klumperink, Eric A.M. and Vaucher, Cicero S. and Nauta, Bram (2002) Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs. IEEE Transactions on Circuits and Systems II: Analog and digital signal processing, 49 (8). pp. 555-566. ISSN 1057-7130

Book

Vaucher, Cicero S. and Nauta, Bram (2002) Architectures for RF Frequency synthesizers. The Kluwer International Series in Engineering and Computer Science, 693 . Kluwer Academic Publishers, Boston, Massachusetts, USA. ISBN 9781402071201

Conference or Workshop Item

Beek, R.C.H van de and Klumperink, E.A.M. and Vaucher, C.S. and Nauta, B. (2002) On Jitter due to Delay Cell Mismatch in DLL-based Clock Multipliers. In: IEEE International Symposium on Circuits and Systems, ISCAS 2002, 26-29 May 2002, Scottsdale, Arizona, USA (pp. pp. 396-399).

Beek, R.C.H. van de and Klumperink, E.A.M. and Vaucher, C.S. and Nauta, B. (2002) Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. In: ProRISC 2002, 13th Workshop on Circuits, Systems and Signal Processing, 28-29 November 2002, Veldhoven, the Netherlands (pp. pp. 190-194).

Beek, R.C.H. van de and Vaucher, C.S. and Leenaerts, D.M.W. and Klumperink, E.A.M. and Nauta, B. (2003) A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS. In: ProRISC 2003, 14th Workshop on Circuits, Systems and Signal Processing, 26-27 November 2003, Veldhoven, the Netherlands (pp. pp. 173-176).

Beek, Remco C.H van de and Vaucher, Cicero S. and Leenaerts, Dominicus M.W. and Pavlovic, Nenad and Mistry, Ketan and Klumperink, Eric A.M. and Nauta, Bram (2003) A 2.5 10 10 GHz Clock Multiplier Unit with 0.22ps RMS Jitter in a 0.18/spl mu/m CMOS Technology. In: IEEE International Solid-State Circuits Conference, ISSCC 2003, 9-13 February 2003, San Francisco, CA, USA (pp. pp. 178-179).

Beek, R.C.H van de and Klumperink, E.A.M. and Vaucher, C.S. and Nauta, B. (2001) Analysis of Random Jitter in a Clock Multiplying DLL Architecture. In: ProRISC 2001, 12th Annual Workshop on Circuits, Systems and Signal Processing, 29-30 November 2001, Veldhoven, the Netherlands (pp. pp. 281-287).

Patent

Beek, Remco Cornelis Herman van de and Klumperink, Eric Antonius Maria and Nauta, Bram and Vaucher, Cicero Silveira (2007) Phase locked loop. Patent.

Nauta, Bram and Beek, Remco C.H van de and Vaucher, Cicero S. (2003) Phase-Locked-Loop With Reduced Clock Jitter. Patent.

Nauta, Bram and Beek, Remco C.H van de and Vaucher, Cicero S. (2005) Phase-Locked-Loop With Reduced Clock Jitter. Patent.

This list was generated on Wed Aug 27 05:18:01 2014 CEST.