A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

Oude Alink, Mark S. and Klumperink, Eric A.M. and Kokkeler, André B.J. and Cheng, Wei and Ru, Zhiyu and Ghaffari, Amir and Wienk, Gerard J.M. and Nauta, Bram (2012) A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL. In: IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012, 17-19 June 2012, Montreal, Canada.

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Abstract:	A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.
Item Type:	Conference or Workshop Item
Copyright:	© 2012 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD) Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/81253
Official URL:	http://dx.doi.org/10.1109/RFIC.2012.6242226
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