Interpretation of MOS transistor mismatch signature through statistical device simulations
Andricciola, Pietro (2011) Interpretation of MOS transistor mismatch signature through statistical device simulations. thesis.
|Abstract:||It is impossible to fabricate two exactly identical transistors. Microscopic device architecture differences lead to slightly different electrical performance, indicated with the term mismatch. Due to the shrinking of the device (more pronounced mismatch), the characterization and modeling of the mismatch became one of the most important part of contemporary chip fabrication/design process.
In this thesis, MOS transistor mismatch was studied through statistical device simulations. In particular, simulated and measured mismatch signatures have been compared. Mismatch signatures are the combination of the standard deviation of the relative drain current mismatch fluctuation over the full bias range and the correlation of the drain current mismatch at any gate bias with the one observed at threshold voltage. These signatures not only allow a quantitative and qualitative analysis but are also suitable for highlighting subtleties that would be overlooked with a purely quantitative approach.
In this thesis, it was demonstrated that interface states between the gate oxide and silicon, if randomized in terms of concentration, energy and position can heavily contribute to the mismatch in the subthreshold region. Moreover, it is shown that the current modeling approach is not able to reproduce the measured signature.
The simulation and analysis method, based on mismatch signatures, were applied to study the mismatch behavior of a different type of device: a Lateral Diffused MOS. These devices show a larger mismatch than bulk MOS theory predicts. It was demonstrated that these devices are heavily affected by interface state fluctuations due to their laterally non-uniform doped channel and that measurements can be seriously hampered by series resistance fluctuations.
Furthermore, the impact of temperature on mismatch has been studied with extensive measurements across four technology nodes and two channel types and dimensions. Although the main indicators of the MOS transistor mismatch performance, do not vary significantly with temperature, the mismatch in subthreshold changes substantially and the relative ION mismatch of individual matched pair can drift. These previously unreported observations imply that circuit designs employing mismatch compensation techniques should adjust the compensation upon a temperature change.
All major findings and outlook for future work are summarized in the conclusive chapter.
Electrical Engineering, Mathematics and Computer Science (EEMCS)
|Link to this item:||http://purl.utwente.nl/publications/79245|
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