Validation of Embedded System Verification Models


Share/Save/Bookmark

Marincic, Jelena and Mader, Angelika and Wieringa, Roel (2011) Validation of Embedded System Verification Models. In: Model-Driven Requirements Engineering Workshop, MoDRE 2011, 29 August 2011, Trento, Italy.

[img]PDF
Restricted to UT campus only
: Request a copy
105Kb
Abstract:The result of a model-based requirements verification shows that the model of a system satisfies (or not) formalised system requirements. The verification result is correct only if the model represents the system adequately. No matter what modelling technique we use, what precedes the model construction are non-formal activities. During these activities the modeller has to learn how the system works, what the requirements are, and to decide what is relevant to model and how to do it. Due to a partly non-formal nature of modelling steps, we do not have a formal proof that the model represents the system adequately. The most we can do is to increase the confidence in the model. In this paper we explore non-formal model validation steps while designing a formal model. On the example of a Uppaal performance model we designed in a company that produces printers, we will show what validation steps were necessary to increase the stakeholders' confidence in the model. Based on this case study, we propose more general, but non-formal model validation steps, that can structure model validation. The steps we propose deal with the same design elements and issues present in other model-based verification activities, therefore can accompany them as well.
Item Type:Conference or Workshop Item
Copyright:© 2011 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/78396
Official URL:http://dx.doi.org/10.1109/MoDRE.2011.6045366
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page