Mapping of Modal Applications given Throughput and Latency Constraints


Geuns, Stefan J. and Hausmans, Joost P.H.M. and Bekooij, Marco J.G. (2011) Mapping of Modal Applications given Throughput and Latency Constraints. In: International Conference on Embedded Computer Systems, SAMOS 2011, 18-21 July 2011, Samos, Greece (pp. pp. 372-379).

[img] PDF
Restricted to UT campus only
: Request a copy
Abstract:Real-time applications such as software defined radios have different reception modes and their real-time requirements are a result of periodic sources and sinks in the form of ADCs and DACs. Tools are under development that automatically translate a sequential specification of a radio application, that often includes nested while loops to describe the modes, into a parallel task graph and map this task graph onto an embedded multiprocessor system. However the specification of strict periodic sources and sinks together with input and output buffers that can respectively overflow or underrun is currently not possible in a sequential programming language. In this paper we will introduce a nested loop program (NLP) language extension that enables the specification of periodic sources and sinks and their buffers in a sequential program. We show that parallelization of such a sequential program poses challenges because the order in which different tasks access the input and output buffers should be maintained in the parallel program. Furthermore, the buffers at the sources and sinks allow destructive writes and non-destructive reads, which causes non-deterministic functional behavior in case the throughput and latency constraint of the application are not met. The other buffers in the task graph block in case no data or space is available. Therefore, the system internals remain functionally deterministic which significantly simplifies debugging and analysis. Furthermore, to guarantee real-time requirements, we show that it is possible to conservatively model an application with nested while loops as a Cyclo-Static Dataflow (CSDF) model. Using this model we can compute a mapping of the task graph, which includes a task to processor assignment, suitable scheduler settings and buffer capacities. By making use of this CSDF model, we can guarantee that sources and sinks can run periodically under the assumption that the used execution times of the tasks are upper bounds.
Item Type:Conference or Workshop Item
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page