Jitter-Power minimization of digital frequency synthesis architectures

Klumperink, Eric and Dutta, Ramen and Ru, Zhiyu and Nauta, Bram and Gao, Xiang (2011) Jitter-Power minimization of digital frequency synthesis architectures. In: IEEE International Symposium on Circuits and Systems, ISCAS 2011, 15-18 May 2011, Rio de Janeiro, Brazil.

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Abstract:	Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture (“ring counter”) over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.
Item Type:	Conference or Workshop Item
Copyright:	© 2011 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/78017
Official URL:	http://dx.doi.org/10.1109/ISCAS.2011.5937527
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