Developing an Integrated Design Strategy for Chip Layout Optimization

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Wits, W.W. and Jauregui Becker, J.M. and Vliet, F.E. van and Riele, G.J. te (2011) Developing an Integrated Design Strategy for Chip Layout Optimization. In: 21st CIRP Design Conference, March 27-29, 2011, Daejeon, South Korea (pp. pp. 55-62).

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Abstract:This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized according to the proposed design rules. This offers chip layout designers an intuitive way to optimize the layout for multiple performance indicators, such as temperature, RF power output or amplifier gain. In a case study, the strategy proposed a chip redesign, boosting overall chip performance without compromising the current cooling infrastructure. The developed integrated design strategy presents a new and time-efficient approach to chip layout optimization and electronics cooling in general.
Item Type:Conference or Workshop Item
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Engineering Technology (CTW)
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Link to this item:http://purl.utwente.nl/publications/76874
Conference URL:http://designweek2011.kaist.ac.kr/cirp/indexcirp.html
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