Testing Superconductor Logic Integrated Circuits


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Joseph, Arun A. and Kerkhoff, Hans G. (2005) Testing Superconductor Logic Integrated Circuits. In: 10th IEEE European Test Symposium (ETS'05), 22-25 May 2005, Talinn, Estonia (pp. pp. 239-244).

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Abstract:Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.
Item Type:Conference or Workshop Item
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/76672
Official URL:http://ati.ttu.ee/ETS/index.php?page=41
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