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Testing Superconductor Logic Integrated Circuits
Joseph, Arun A. and Kerkhoff, Hans G. (2005) Testing Superconductor Logic Integrated Circuits. In: 10th IEEE European Test Symposium (ETS'05), 22-25 May 2005, Talinn, Estonia.
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| Abstract: | Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits. |
| Item Type: | Conference or Workshop Item |
| Faculty: | Electrical Engineering, Mathematics and Computer Science (EEMCS) |
| Research Group: | |
| Link to this item: | http://purl.utwente.nl/publications/76672 |
| Official URL: | http://ati.ttu.ee/ETS/index.php?page=41 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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