A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

Gao, Xiang and Klumperink, Eric and Socci, Gerard and Bohsali, Mounhir and Nauta, Bram (2010) A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power. In: IEEE Symposium on VLSI Circuits, VLSI 2010, 16-18 June 2010, Hawai, Honolulu.

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Abstract:	A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
Item Type:	Conference or Workshop Item
Copyright:	© 2010 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/75865
Official URL:	http://dx.doi.org/10.1109/VLSIC.2010.5560323
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