Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

Dutta, R. and Bhattacharyya, T.K. and Gao, X. and Klumperink, E.A.M. (2010) Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. In: 23th International Conference on VLSI Design, VLSID 2010, 3-7 Jan 2010, Bangalore, India.

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Abstract:	In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.
Item Type:	Conference or Workshop Item
Copyright:	© 2010 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/75789
Official URL:	http://dx.doi.org/10.1109/VLSI.Design.2010.78
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