Designing a dataflow processor using CλaSH


Niedermeier, Anja and Wester, Rinse and Rovers, Kenneth and Baaij, Christiaan and Kuper, Jan and Smit, Gerard (2010) Designing a dataflow processor using CλaSH. In: 28th Norchip Conference, NORCHIP 2010, 15-16 November 2010, Tampere, Finland (pp. p. 69).

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Abstract:In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.
Item Type:Conference or Workshop Item
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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