Balanced comparator fabricated in ramp edge technology


Sonnenberg, A.H. and Gerritsma, G.J. and Rogalla, H. (1999) Balanced comparator fabricated in ramp edge technology. Physica C: Superconductivity, 326-32 . pp. 12-15. ISSN 0921-4534

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Abstract:One of the basic elements of RSFQ circuits is the balanced comparator. We have fabricated and tested a balanced comparator in a three HTS layer technology. The junctions and inductances are located on a buried ground plane in order to reduce the inductance values. We have chosen for a buried ground plane in order to avoid heating the ramp edge junction to deposition temperatures. Correct operation of the balanced comparator has been verified by dc measurements of the switching properties. The gray zone of switching has been measured as a function of temperature and operation frequency.
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Copyright:© 1999 Elsevier
Science and Technology (TNW)
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Metis ID: 128835