Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

Vandenbossche, Eric and De Keukeleire, Catherine and Wolf de, Marc and Hove van, Hugo and Witters, Johan (1998) Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors. Microelectronics Reliability, 38 (6-8). pp. 1097-1101. ISSN 0026-2714

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Abstract:	This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.
Item Type:	Article
Copyright:	© 1998 Elsevier
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Semiconductor Components (SC)
Link to this item:	http://purl.utwente.nl/publications/73812
Official URL:	http://dx.doi.org/10.1016/S0026-2714(98)00115-2
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