A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS

Drago, Salvatore and Leenaerts, Dominicus M.W. and Nauta, Bram and Sebastiano, Fabio and Makinwa, Kofi A.A. and Breems, Lucien J. (2010) A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS. IEEE Journal of Solid-State Circuits, 45 (7). pp. 1305-1315. ISSN 0018-9200

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Abstract:	Abstract The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm2 and draws 200 μA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.
Item Type:	Article
Copyright:	© 2010 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/73660
Official URL:	http://dx.doi.org/10.1109/JSSC.2010.2049458
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