Novel test structures for temperature budget determination during wafer processing


Share/Save/Bookmark

Faber, E.J. and Wolters, R.A.M. and Schmitz, J. (2010) Novel test structures for temperature budget determination during wafer processing. In: IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010, 22-25 Mar 2010, Hirosjima, Japan (pp. pp. 30-33).

open access
[img]
Preview
PDF
1MB
Abstract:Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100-200°C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.
Item Type:Conference or Workshop Item
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/72452
Official URL:http://dx.doi.org/10.1109/ICMTS.2010.5466867
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page