Spur-reduction techniques for PLLs using sub-sampling phase detection

Gao, Xiang and Klumperink, Eric A.M. and Socci, Gerard and Bohsali, Mounhir and Nauta, Bram (2010) Spur-reduction techniques for PLLs using sub-sampling phase detection. In: IEEE International Solid-State Circuits Conference, ISSCC 2010, 7-11 Feb 2010, San Francisco, USA.

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Abstract:	A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18-μm CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.
Item Type:	Conference or Workshop Item
Copyright:	© 2010 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/72398
Official URL:	http://dx.doi.org/10.1109/ISSCC.2010.5433841
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