Reconfigurable Multicore Architectures for Streaming Applications
Smit, Gerard J.M. and Kokkeler, André B.J. and Rauwerda, Gerard K. and Jacobs, Jan W.M. (2009) Reconfigurable Multicore Architectures for Streaming Applications. In: G. Nicolescu & P.J. Mosterman (Eds.), Model-Based Desing for Embedded Systems. CRC Press, Boca Raton, Florida, pp. 323-350. ISBN 9781420067842
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|Abstract:||This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bitlevel reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains.
We take a holistic approach, which means that all aspects of systems design need to be addressed simultaneously in a systematic way. This is key for an efficient overall solution, because an interesting optimization in a small corner of the design might lead to inefficiencies in the overall design.
We introduce streaming applications and multi-core architectures We present key design criteria for streaming applications and give a multi-dimensional classification of architectures for streaming applications. For each category one or more sample architectures are presented.
|Item Type:||Book Section|
|Copyright:||© 2009 CRC|
Electrical Engineering, Mathematics and Computer Science (EEMCS)
|Link to this item:||http://purl.utwente.nl/publications/72178|
|Export this item as:||BibTeX|
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