70 input, 20 nanosecond pattern classifier


Masa, P. and Hoen, K. and Wallinga, H. (1994) 70 input, 20 nanosecond pattern classifier. In: IEEE International Conference on Neural Networks, 1994, 27 June - 2 July 1994, Orlando, FL, USA (pp. pp. 1854-1859).

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Abstract:A CMOS neural network integrated circuit is discussed, which was designed for very high speed applications. This full-custom, mixed analog-digital chip implements a fully connected feedforward neural network with 70 inputs, 6 hidden layer neurons and one output neuron. The neurons perform inner product operation and have a sigmoid-like activation function. The 70 network inputs and the neural signal processing are analog, the synaptic weights are digitally programmable with 5 bit (4 bits+sign) precision. The synaptic weights are stored on on-chip static RAM cells. The combination of analog and digital techniques results in unique computing power with ease of use. Programming can easily be performed with the help of a spreadsheet or other suitable interface program from a PC. The resolution of the input signals is mainly determined by the signal to noise ratio which lies typically between 8-12 bits. Therefore the equivalent input bandwidth can be as high as 28-42 Gbits/second. The system is designed for very high speed vector classification and the feasibility of a single chip neural network photon trigger for nuclear research is shown. Because of the fully parallel architecture and the fast analog signal processing the network achieves unique computing performance and classifies up to 70 dimensional vectors within 20 nanoseconds, performing 20 billion (2×1010) multiply-and-add operations per second. The circuit occupies 10×9 mm2 silicon area with 1.5 μm CMOS process and dissipates only 1 W at 5 V supply.
Item Type:Conference or Workshop Item
Copyright:© 1994 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/71995
Official URL:https://doi.org/10.1109/ICNN.1994.374440
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