Testability enhancement of a basic set of CMOS cells

Share/Save/Bookmark

Rullan, M. and Oliver, J. and Ferrer, C. and Blom, F.C. (1994) Testability enhancement of a basic set of CMOS cells. Quality and Reliability Engineering International, 10 (4). pp. 279-288. ISSN 0748-8017

open access
[img]
Preview
PDF
908kB
Abstract:Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design.
Item Type:Article
Copyright:© 1994 Wiley InterScience
Research Group:
Link to this item:http://purl.utwente.nl/publications/71077
Official URL:http://dx.doi.org/10.1002/qre.4680100406
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page