A 200 ¹A Duty-Cycled PLL for Wireless Sensor Nodes

Drago, Salvatore and Leenaerts, Domine and Nauta, Bram and Sebastiano, Fabio and Makinwa, Kofi and Breems, Lucien (2009) A 200 ¹A Duty-Cycled PLL for Wireless Sensor Nodes. In: 35th European Solid-State Circuits Conference, ESSCIRC '09, 14-18 Sept 2009, Greece, Athene.

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Abstract:	A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 ¹A from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/69822
Official URL:	http://dx.doi.org/10.1109/ESSCIRC.2009.5325979
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