An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models
Hansson, Andreas and Goossens, Kees (2009) An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models. In: 7th IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis, 11-16 October 2009, Grenoble,France.
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|Abstract:||A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate. Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint
streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock.
In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple
communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.
|Item Type:||Conference or Workshop Item|
|Copyright:||© 2009 ACM|
Electrical Engineering, Mathematics and Computer Science (EEMCS)
|Link to this item:||http://purl.utwente.nl/publications/69770|
|Export this item as:||BibTeX|
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