A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

Gao, X. and Klumperink, Eric A.M. and Bohsali, Mounhir and Nauta, Bram (2009) A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2. IEEE Journal of Solid-State Circuits, 44 (12). pp. 3253-3263. ISSN 0018-9200

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Abstract:	This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 mm
Item Type:	Article
Copyright:	© 2009 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/69683
Official URL:	http://dx.doi.org/10.1109/JSSC.2009.2032723
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