Gate current for p+-poly PMOS devices under gate injection conditions
Hof, A.J. and Holleman, J. and Woerlee, P.H. (2001) Gate current for p+-poly PMOS devices under gate injection conditions. In: 4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2001, 28-30 Nov 2001, Veldhoven, The Netherlands.
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|Abstract:||In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the influence of the oxide thickness on the IV-characteristics under gate injection for p+-poly PMOS devices is studied. For this purpose, devices were fabricated with oxide thickness ranging from 5 to 20 nm.
All other processing steps were identical for these devices. The gate current for negative gate voltage was measured on these devices and the oxide electric field was extracted from CV-measurements. When the measured currents are plotted as a function of the extracted oxide electric field the coincide for all oxide thicknesses. The measured currents can be modeled neither by Fowler-Nordheim tunneling nor by valence band tunneling. An attempt to model the measured current with minority carrier tunneling also fails. It is concluded that the measured gate currents for negative gate voltage for p+-poly PMOS devices is independent of the gate oxide thickness for devices with identical gate processing. In this case, the gate current only depends on the applied oxide electric field.
For future modeling, the poly gate cannot be assumed to be uniformly doped in the lateral directions as was done for this study. Furthermore, a different tunneling mechanism needs to be considered.
|Item Type:||Conference or Workshop Item|
Electrical Engineering, Mathematics and Computer Science (EEMCS)
|Link to this item:||http://purl.utwente.nl/publications/67779|
|Export this item as:||BibTeX|
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