Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs

Sowariraj, M.S.B. and Kuper, F.G. and Salm, C. and Mouthaan, A.J. and Smedes, T. (2002) Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs. In: Proceedings of the 5th annual workshop on Semiconductors Advances for Future Electronics SAFE 2002, 27-28 November 2002, Veldhoven, The Netherlands.

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Abstract:	In this paper we present a systematic study on the effect of process and layout variation for groundedgate NMOSTs and LVTSCRs in a 0.18m technology under negative non-socketed Charged Device Model (CDM) stress. A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance of LVTSCRs can be as good as that of ggNMOSTs under CDM stresses.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Semiconductor Components (SC)
Link to this item:	http://purl.utwente.nl/publications/67768
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