Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy

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Sowariraj, M.S.B. and Smedes, Theo and Salm, Cora and Mouthaan, Ton and Kuper, Fred G. (2003) Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy. Microelectronics Reliability, 43 (9-11). pp. 1569-1575. ISSN 0026-2714

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Abstract:With sownscaling of device dimensions and increased usage of automated handlers, Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major readon for field returns in the Integrated Circuit (IC) industry. In the case of CDM stress, the IC is both the source of static charge and part od the discharge path. Hence CDM test results are greatly affected by the nature of the package, pin position and the location of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to find the actual discharge current flowing through the die and the protection structures for different packages and pin positions. From this general protection strategy for CDM discharges, independent of the IC layout design is developed.
Item Type:Article
Copyright:© 2003 Elsevier
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67734
Official URL:http://dx.doi.org/10.1016/S0026-2714(03)00276-2
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