Progressive degradation in a-Si: H/SiN thin film transistors

Share/Save/Bookmark

Merticaru, A.R. and Mouthaan, A.J. and Kuper, F.G. (2003) Progressive degradation in a-Si: H/SiN thin film transistors. Thin Solid Films, 427 (1-2). 60-66. ISSN 0040-6090

[img] PDF
Restricted to UT campus only
: Request a copy
195kB
Abstract:In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region.
Item Type:Article
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Link to this item:http://purl.utwente.nl/publications/67731
Official URL:http://dx.doi.org/10.1016/S0040-6090(02)01245-2
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page