A 3-D circuit model to evaluate CDM performance of ICs


Sowariraj, M.S.B. and Jong, P.C. de and Salm, C. and Mouthaan, A.J. and Kuper, F.G. (2005) A 3-D circuit model to evaluate CDM performance of ICs. Microelectronics Reliability, 45 (9-11). pp. 1425-1429. ISSN 0026-2714

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Abstract:This paper presents a physical description of the static charge flow through an IC during a CDM event. Based on this description, an equivalent 3-D circuit to model the complete IC under CDM stress is proposed. The model takes into account various factors like package parasitics, substrate resistance, parasitic contacts of the circuit elements with the substrate, bus line resistances, distribution of protection devices. It allows studying the influence of these factors on the voltage transients seen across the gate-oxides of MOS transistors. CDM measurements on an IC with rail based protection showed gate-oxide failure at the MOS transistors in the internal core circuitry. The proposed circuit model is applied to study the voltage transients between the internal MOS transistors gate and local substrate during CDM stress and thereby explain the reason for the observed gate-oxide failure. It is found that VSS line contact distribution with the substrate rail enhances CDM robustness, provided the power lines (VSS and VDD line) are well clamped to each other.
Item Type:Article
Copyright:© 2005 Elsevier
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/67713
Official URL:https://doi.org/10.1016/j.microrel.2005.07.066
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