Delay 25 an ASIC for timing adjustment in LHC

Furtado, H. and Schrader, J.H.R. and Marchioro, A. and Moreira, P. (2005) Delay 25 an ASIC for timing adjustment in LHC. In: 11th Workshop on Electronics for LHC and future Experiments, 12-16 September 2005, Heidelberg, Germany.

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Abstract:	A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/67691
Official URL:	http://cdsweb.cern.ch/record/920425
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