A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

Beek van de, Remco C.H and Vaucher, Cicero S. and Leenaerts, Domine M.W. and Klumperink, Eric A.M. and Nauta, Bram (2004) A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 39 (11). pp. 1862-1872. ISSN 0018-9200

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Abstract:	This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.
Item Type:	Article
Copyright:	© 2004 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/67655
Official URL:	http://dx.doi.org/10.1109/JSSC.2004.835833
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