5.5-V I/O in a 2.5-V 0.25-µm CMOS technology


Annema, Anne-Johan and Geelen, Govert J.G.M. and Jong, Peter C. de (2001) 5.5-V I/O in a 2.5-V 0.25-µm CMOS technology. IEEE journal of solid-state circuits, 36 (3). pp. 528-538. ISSN 0018-9200

[img] PDF
Restricted to UT campus only
: Request a copy
Abstract:A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages
Item Type:Article
Copyright:© 2001 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67625
Official URL:https://doi.org/10.1109/4.910493
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page