Low-temperature fabricated TFTs on polysilicon stripes


Brunets, I. and Holleman, J. and Kovalgin, A.Y. and Boogaard, A. and Schmitz, J. (2009) Low-temperature fabricated TFTs on polysilicon stripes. IEEE Transactions on Electron Devices, 56 (8). pp. 1637-1644. ISSN 0018-9383

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Abstract:This paper presents a novel approach to make highperformance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material.
The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/V • s (NMOS) and 128 cm2/V • s (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized.
The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration.
Item Type:Article
Copyright:© 2009 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/67556
Official URL:https://doi.org/10.1109/TED.2009.2023021
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