A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS


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Beek van de, R.C.H. and Vaucher, C.S. and Leenaerts, D.M.W. and Klumperink, E.A.M. and Nauta, B. (2003) A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS. In: ProRISC 2003, 14th Workshop on Circuits, Systems and Signal Processing, 26-27 November 2003, Veldhoven, the Netherlands.

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Abstract:Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast
phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.
Item Type:Conference or Workshop Item
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/67446
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