Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch


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Beek, R.C.H. van de and Klumperink, E.A.M. and Vaucher, C.S. and Nauta, B. (2002) Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. In: ProRISC 2002, 13th Workshop on Circuits, Systems and Signal Processing, 28-29 November 2002, Veldhoven, the Netherlands (pp. pp. 190-194).

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Abstract:This paper describes the jitter problem in
DLL-based clock multipliers that arises due to stochastic
mismatch in the delay cells that are used in the Voltage Controlled
Delay Line of the DLL [1]. An analysis is presented
that relates the stochastic spread of the delay of the cells to
the output jitter of the clock multiplier. This analysis shows
that relative time deviations are highest in the middle of the
Delay Line and proportional to the square root of the frequency
multiplication factor of the structure. A circuit design
technique, called Impedance Level Scaling, is presented
that allows the designer to optimize the noise and mismatch
behavior of a circuit independent of other specifications such
as speed and linearity. Applying this technique on delay cell
design yields a direct trade-off between noise induced jitter
and power usage, and between stochastic mismatch induced
jitter and power usage.
Item Type:Conference or Workshop Item
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67440
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Metis ID: 207349