Trends and challenges in VLSI technology scaling towards 100 nm


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Rusu, S. and Sachdev, M. and Svensson, C. and Nauta, B. (2002) Trends and challenges in VLSI technology scaling towards 100 nm. In: Design Automation Conference, DAC 2002, 7-11 January 2002, Bangladore, India (pp. pp. 16-17).

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Abstract:Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solutions
Item Type:Conference or Workshop Item
Copyright:© 2002 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67433
Official URL:http://dx.doi.org/10.1109/ASPDAC.2002.994875
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