Transmission Lines in CMOS: An Explorative Study

Klumperink, E.A.M. and Kreienkamp, R. and Ellermeyer, T. and Langmann, U. (2001) Transmission Lines in CMOS: An Explorative Study. In: ProRISC 2001, 12th Annual Workshop on Circuits, Systems and Signal Processing, 29-30 November 2001, Veldhoven, the Netherlands.

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Abstract:	On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important transmission line properties like characteristic impedance, propagation velocity and loss in a 0.18 micron CMOS Technology. Both metal losses and substrate losses are modeled. Special attention is paid to the effect of the Silicon substrate, in particular to the so called “slow-wave mode” that can occur in the Si-SiO2 system.
Item Type:	Conference or Workshop Item
Copyright:	© 2001 Technology Foundation STW
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/67426
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