The Chameleon Architecture for Streaming DSP Applications

Share/Save/Bookmark

Smit, Gerard J.M. and Kokkeler, André B.J. and Wolkotte, Pascal T. and Hölzenspies, Philip K.F. and Burgwal van de, Marcel D. and Heysters, Paul M. (2007) The Chameleon Architecture for Streaming DSP Applications. EURASIP Journal on Embedded Systems, 2007 . p. 78082. ISSN 1687-3955

[img]
Preview
PDF
1088Kb
Abstract:We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.
Item Type:Article
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67115
Official URL:http://dx.doi.org/10.1155/2007/78082
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 242171