Using an FPGA for Fast Bit Accurate SoC Simulation


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Wolkotte, P.T. and Hölzenspies, P.K.F. and Smit, G.J.M. (2007) Using an FPGA for Fast Bit Accurate SoC Simulation. In: 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07) - 14th Reconfigurable Architecture Workshop (RAW 2007), 26-30 March 2006, Long Beach, CA, USA (pp. p. 167).

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Abstract:In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.
Item Type:Conference or Workshop Item
Copyright:© 2007 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/67065
Official URL:http://dx.doi.org/10.1109/IPDPS.2007.370374
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Metis ID: 242165