The Construction of Verification Models for Embedded Systems


Mader, A.H. and Wupper, H. and Boon, M. (2007) The Construction of Verification Models for Embedded Systems. [Report]

open access
Abstract:The usefulness of verification hinges on the quality of the verification model. Verification is useful if it increases our confidence that an artefact bahaves as expected. As modelling inherently contains non-formal elements, the qualityof models cannot be captured by purely formal means. Still, we argue that modelling is not an act of irrationalism and unpredictable geniality, but follows rational arguments, that often remain implicit. In this paper we try to identify the tacit rationalism in the model construction as performed by most people doing modelling for verification. By explicating the different phases, arguments, and design decisions in the model construction, we try to develop guidelines that help to improve the process of model construction and the quality of models.
Item Type:Report
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Faculty of Behavioural, Management and Social sciences (BMS)
Research Group:
Link to this item:
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page

Metis ID: 242790