An Optimal Architecture for a DDC

Bijlsma, Tjerk and Wolkotte, Pascal T. and Smit, Gerard J.M. (2006) An Optimal Architecture for a DDC. In: 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - 12th Reconfigurable Architecture Workshop, RAW 2006, 25-29 April 2006, Rhodes Island, Greece.

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Abstract:	Digital down conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algorithm consists of two simple cascading integrating comb (CIC) filters and a finite input response (FIR) filter preceded by a modulator that is controlled with a numeric controlled oscillator (NCO). Implementations of the algorithm have been made for five architectures, two application specific integrated circuits (ASIC), a general purpose processor (GPP), a field programmable gate array (FPGA), and the Montium tile processor (TP). All architectures are functionally capable of performing the algorithm. The differences between the architectures are their performance, flexibility and energy consumption. In this paper, we compared the energy consumption of the architectures when performing the DDC algorithm. The ASIC is the best solution if digital down conversion is constantly required. When digital down conversion is needed only parts of the time, the Altera Cyclone II is the best solution due to its smaller technology size. In the spare time, the reconfigurable architectures can be reconfigured for other tasks of today's multimedia devices.
Item Type:	Conference or Workshop Item
Copyright:	© 2006 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/66589
Official URL:	http://dx.doi.org/10.1109/IPDPS.2006.1639440
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