An Energy and Performance Exploration of Network-on-Chip Architectures

Banerjee, Arnab and Wolkotte, Pascal T. and Mullins, Robert D. and Moore, Simon W. and Smit, Gerard J.M. (2009) An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17 (3). pp. 319-329. ISSN 1063-8210

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Abstract:	In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs.
Item Type:	Article
Copyright:	© 2009 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/65433
Official URL:	http://dx.doi.org/10.1109/TVLSI.2008.2011232
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