Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Schinkel, D. and Mensink, E. and Klumperink, E.A.M. and van Tuijl, A.J.M. and Nauta, B. (2009) Low-Power, High-Speed Transceivers for Network-on-Chip Communication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17 (1). pp. 12-21. ISSN 1063-8210

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Abstract:	Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
Item Type:	Article
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/65427
Official URL:	http://dx.doi.org/10.1109/TVLSI.2008.2001949
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