Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

Gao, X. and Klumperink, E.A.M. and Geraedts, P.F.J. and Nauta, B. (2009) Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. IEEE Transactions on Circuits and Systems II - Express Briefs, 56 (2). pp. 117-121. ISSN 1549-7747

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Abstract:	This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed.
Item Type:	Article
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/65426
Official URL:	http://dx.doi.org/10.1109/TCSII.2008.2010189
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