An Automated Design-flow for FPGA-based Sequential Simulation

Wolkotte, P.T. and Rutgers, J. H. and Hölzenspies, P.K.F. and Westmijze, M. and Blumink, R. and Smit, G.J.M. (2008) An Automated Design-flow for FPGA-based Sequential Simulation. In: ProRISC 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing, 27-28 November 2008, Veldhoven, the Netherlands.

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Abstract:	In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/65230
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