Discrete wavelet transform on dynamically reconfigurable hardware.

Walters, K.H.G. and Smit, G.J.M. and Gerez, S.H. (2008) Discrete wavelet transform on dynamically reconfigurable hardware. In: On-Board Payload Data Compression Workshop 2008, 26-27 Jun 2008, Noordwijk.

Preview

PDF
338Kb

Abstract:	The increasing amount of data produced in satellites poses a problem for the limited data rate of its downlink. This discrepancy is solved by introducing more and more processing power on-board to compress data to a satisfiable rate. Currently, this processing power is often provided by custom-off-the-shelf hardware. These architectures introduce problems when they are scaled up. To deal with the ever increasing data rate of the newest sensors and still be within the same power and thermal constraints, new architectures are being examined. In this paper we will describe one of these new architectures, the Montium tile processor, and we show how a well-known algorithm, the CCSDS 9/7 integer discrete wavelet transform (DWT), can be mapped to this architecture. Furthermore, some improvements are discussed that can make the Montium and reconfigurable architectures in general, an even better platform to support algorithms like the DWT.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/64914
Export this item as:	BibTeX EndNote HTML Citation Reference Manager

Show download statistics for this publication

Repository Staff Only: item control page

Metis ID: 254883