A 1.9 uW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC


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Elzakker, Michel van and Tuijl, Ed van and Geraedts, Paul and Schinkel, Daniël and Klumperink, Eric and Nauta, Bram (2008) A 1.9 uW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC. In: IEEE International Solid-State Circuits Conference, ISSCC 2008, 3-7 February 2008, San Francisco, CA, USA (pp. 244-245+610).

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Abstract:A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.
Item Type:Conference or Workshop Item
Copyright:© 2008 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/64872
Official URL:http://dx.doi.org/10.1109/ISSCC.2008.4523148
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Metis ID: 251074