Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core


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Smit, L.T. and Rauwerda, G.K. and Molderink, A. and Wolkotte, P.T. and Smit, G.J.M. (2007) Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. In: International Conference on Field Programmable Logic and Applications, FPL 2007, 27-29 August 2007, Amsterdam, Netherlands (pp. pp. 562-566).

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Abstract:This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
Item Type:Conference or Workshop Item
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/64324
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