A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

Louwsma, S.M. and Tuijl van, A.J.M. and Vertregt, M. and Nauta, B. (2007) A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR. In: Custom Integrated Circuits Conference, CICC 2007, 16-19 Sept 2007, San Jose, CA USA.

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Abstract:	Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.
Item Type:	Conference or Workshop Item
Copyright:	© 2007 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/64288
Official URL:	http://dx.doi.org/10.1109/CICC.2007.4405745
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