Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

Schinkel, D. and Mensink, E. and Klumperink, E.A.M. and Tuijl van, A.J.M. and Nauta, B. (2007) Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. In: IEEE International Solid-State Circuits Conference, ISSCC 2007, 11-15 February 2007, San Francisco, CA, USA.

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Abstract:	A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time
Item Type:	Conference or Workshop Item
Copyright:	© 2007 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/64054
Official URL:	http://dx.doi.org/10.1109/ISSCC.2007.373420
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