Multi-phase clock generation for multi-path poly-phase transceivers


Gao, X. (2006) Multi-phase clock generation for multi-path poly-phase transceivers. [Masters Thesis]

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Abstract:Software Defined Radio is an attractive idea for future radio transceiver systems due to its potential advantages like: convenience, low cost, and short time to market. However, some problems still need to be solved before SDR can go to the market. One of them is harmonic rejection. Flexible high-Q RF filtering is difficult to realize on chip and it takes large chip area. Instead of using a filter, a poly-phase multi-path technique has been developed that can suppress harmonics and image components. The research presented in this thesis is originally motivated by the need of precise multi-phase clocks for this harmonics and image rejection technique.
For multi-phase clock generation, using a DLL and using a shift register are two well known methods. The method using a shift register is a brute force way to generate multi-phase clock and at first glance seems to have more power consumption than a DLL. This work makes a solid comparison between these two methods. Comparison results show that a shift register actually has better jitter and power performance than a DLL, when both are implemented with CML style circuits. A shift register also has other advantages like shorter settling time, reduced design complexity and wider operating frequency range. However, the maximum achievable working frequency of a shift register is lower than a DLL. Therefore, a shift register should be used at low frequency and a DLL should be used at high frequency where the shift register can not work.
For a conventional multi-phase clock generation DLL, one disadvantage is that the jitter accumulates from one phase clock to the other phase clock. In this work, a new DLL architecture is proposed which can reduce this jitter accumulation effect. In addition, the proposed architecture increases the tuning range of the DLL
For a conventional multi-phase clock generation shift register, one drawback is that it needs to work at N times higher than the frequency of interest for N-phase clock generation. In this work, a new shift register architecture is proposed which can decrease the working frequency of the major function block in the shift register and also bring other improvements.
Item Type:Masters Thesis
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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